The use of conventional diffused junction N and P-Channel Metal Oxide Semiconductor Field Effect Transistors, (hereinafter (MOSFETS), in functional seriesed combination to form Complimentary Metal Oxide Semiconductor, (hereinafter (CMOS)), field effect transistor device systems is well known, as are the benefits associated with the use thereof. Said benefits include enabling realization of very low power consumption digital switching logic circuitry such as is found in electronic wrist watches which run for years on one small battery.
Briefly, a conventional (MOSFET) is comprised of N or P-type semiconductor substrate, in the surface region of which are formed regions of oppositely doped material, separated by a distance therebetween in said semiconductor substrate. The regions of oppositely doped material are termed the "Source" and "Drain" and the distance therebetween is termed the "Channel Region". Diffused rectifying junctions are thus caused to exist at the ends of the channel region, both at the source and at the drain. Continuing, atop the channel region surface is present an insulating material, such as silicon dioxide, atop of which insulating material is present a "Gate" which is made from an electrically conductive material. Application of a voltage from the drain-to-source of a proper polarity, simultaneous with the application of a gate-to-source voltage of a proper polarity causes the channel region to "invert" and become of a doping type similar to that in the source and drain regions, thereby providing a conductive pathway between said drain and source. That is, application of a gate-to-source voltage modulates the conductivity of, hence flow of current between, the drain and source. Because the resistivity of the insulating material is high, very little gate current is required to effect modulation of said drain to source current flow. As mentioned above, conventional (CMOS) device systems comprise a seriesed combination of electrically connected N and P-channel (MOSFET) devices, formed on P and N-type semiconductor respectively. To form (CMOS) the drain of an N-channel (MOSFET) device is electrically connected to the drain of the a P-channel (MOSFET) device and the source of the P-channel device is connected to a positive (+Vdd), while the source of the N-channel (MOSFET) device is connected to a lower voltage (-Vss), typically ground. In use, a relatively low, (approximately the voltage appplied to the source of the N-channel (MOSFET) device), gate voltage applied simultaneously to the gates of said electrically connected devices modulates the P channel device so that it conducts, while having no channel conductivity increasing effect on the N channel device. Similarly, simultaneous application of a relatively high, (with respect to the voltage applied to the source of the N-channel (MOSFET) device, eg. approximately +Vdd), gate voltage affects the N and P channel devices in an opposite manner. That is the N-channel device channel inverts and conductivity is effectively increased from the associated source to drain, while the P-channel device channel conductivity is not increased. The result being that varying gate-to-source voltage from relatively low, (-Vss), to relatively high, (+Vdd), causes the voltage present at the electrically connected N and P-channel device drains, which terminal is essentially electrically isolated from the gates, to vary essentially between that applied to the source of the P-channel device, (+Vdd), and that applied to the source of the N-channel device, (typically, but not necessarily, ground potential), respectively. Said (CMOS) is then inverting between input and output. As mentioned above, (CMOS) switching is effected with very little gate current flow, as the insulating material between the gate and the semiconductor is of a very high resistance, (eg. ten-to-the-forteenth ohms or higher). As well, drain to source current flows only briefly at the switching point when both devices are momentarily conducting. This is because current cannot flow through an electrically connected series of (MOSFETS) when either thereof does not have a conducting inverted channel present. Conventional (MOSFET) and (CMOS) operational characteristics are described in numerous circuit design texts such as "Basic Integrated Circuit Engineering" by Hamilton and Howard, McGraw-Hill; 1975.
While conventional (CMOS) device systems provide benefits, fabrication thereof is by diffused junction technology which requires many steps, including many photoresist procedures, sequential mask alignments, and various etches. It is to be appreciated that each such step involves an efficiency factor, and thereby introduces defects leading to decreased yield of working devices on a fabrication substrate. In some instances the ratio of working to the total devices attempted on a substrate can be fifty (50%) percent or even less. For instance if a procedure step carries a ninety (90%) percent efficiency factor, (an extremely low value used for demonstrative purposes), after two such steps only eighty-one (81%) percent of the devices will be operational. After six (6) such steps, it should be appreciated, the effective yield of working devices will be less than fifty (50%) percent. Obviously, if the number of steps in a fabrication procedure can be reduced the yield of working devices can be increased. However, conventional diffused junction technology does not allow reducing the number of steps involved in a fabrication procedure below a relatively large number.
A fabrication procedure which requires a reduced number fabrication procedure steps to provide functionally equivalent (CMOS) device systems would therefore be of utility.
With that in mind it is to be appreciated that an alternative to conventional diffused junction technology is that of Schottky barrier junction technology. The present invention utilizes said schottky barrier junction technology in a fabrication procedure requiring a relatively few number of steps to provide Schottky Barrier (CMOS) device systems and a single substrate type single device equivalent to (CMOS).
A Schottky barrier is essentially a rectifying junction formed between, for instance, a nonsemiconductor (eg. metal or metal compound), and a doped semiconductor. Such a junction exhibits a "built-in" Schottky barrier potential which serves to inhibit current conduction when a voltage of one polarity is applied thereto, and allows current to flow more easily when an opposite polarity voltage is applied thereto. In important respects then, a Schottky barrier acts much like a diffused junction rectifier.
A Search of relevant references has provided an article by Hogeboom and Cobbold, titled "Etched Schottky Barrier (MOSFETS) Using A Single Mask". Said article describes the fabrication of a P-Channel (MOSFET) on N-type silicon with aluminum forming the rectifying junction schottky barrier source and drain junctions. (Note that aluminum does not form a rectifying junction schottky barrier on P-type silicon hence is not an appropriate metal for use in realization of N-channel Schottky barrier (MOSFETS)). Said article also describes both N and P-Channel conventional diffused junction (MOSFETS) fabricated using a single mask, but which required a diffusion of a dopant, hence, did not operate based upon schottky barrier junction presence. Aluminum present provided non-rectifying contact to diffused regions as in conventional (MOSFETS). This paper also suggests the use of vanadium to form source and drain regions. It is also noted that this paper describes use of a silicon dioxide undercutting etch which facilitates self delineation of fabricated devices when essentially line-of-sight aluminum deposition is achieved. (The silicon etchant taught is a mixture of fifty (50) parts acetic acid, thirty (30) parts nitric acid, twenty (20) parts hydrofluoric acid and one (1) part aniline). A Patent to Welch, U.S. Pat No. 4,696,093 describes a procedure for fabricating Schottky barrier (MOSFETS), including an approach requiring only one-mask and one-etch and the use of chromium, (which after application to silicon is subjected to an annealing procedure to form chromium disilicide), as the metal used to form rectifying source and drain Schottky barrier junctions. A Masters Thesis presented by James D. Welch at the University of Toronto in 1974 titled "Design and Fabrication of Sub-Micron Channel MOS Transistors by Double Ion-Implantation" mentions Schottky barrier rectifying junctions discovered to exist after a thirty (30) minute, six-hundred-fifty (650) degree centigrade anneal of chromium present on the back, unpolished, side of an N-type silicon substrate. The reverse breakdown voltage of said rectifying junctions was found to be upwards of eighty (80) volts. However, said thesis work did not include investigation of annealing deposited chromium on P-type silicon. A paper by Lebedev and Sultanov, in Soviet Physics Semiconductors, Vol. 4, No. 11, May 1971, pages 1900-1902 teaches the chromium diffused into P-type Silicon at high, (eg. twelve hundred (1200) degrees centigrade), for long periods of time, (eg. twenty (20) to fifty (50) hours), dopes said P-type silicon N-type. Nothing, however, is stated regarding the properties of chromium disilicide formed by annealing a thin film of chromium which has been deposited upon said P-type silicon silicon at lower temperatures. A paper by Lepselter and Sze, titled "SB-IGFET: An Insulated-Gate Field Effect Transistor Using Schottky Barrier Contacts for Source and Drain", in the Proceedings of the IEEE, August 1968, pages 1400 through 1402 describes a P-Channel schottky barrier insulated gate field effect transistor, (ie. IGFET), fabricated using schottky barrier junctions for source and drain. Said IGFET utilized platinum silicide in the formation of the source and drain junctions. It is stated that during operation the source junction of the device is reverse biased in the inverted channel region and that reverse leakage or tunneling current therethrough is what applied gate voltage modulates. The Lepselter et al. article however, makes no mention of the use of Schottky barriers to form N-Channel devices on P-type silicon. In fact, owing to the rather large reverse barrier height difference between platinum silicide and N-type silicon, (ie. 0.85 ev), and between platinum silicide and P-type silicon, (ie. 0.25 ev), it is unlikely that N-channel devices would be operablle, or even if they were, that an effective (CMOS) device system could be achieved using platinum-silicide to form both N and P-channel devices. This is because the (MOSFET) devices in a (CMOS) device system must have essentially symetrical and complimentary operational characteristics to provide efficient switching capability. The Lepselter et al. article provides an equation for calculating tunneling current density through a reverse biased Schottky barrier junction: ##EQU1## where E is the electric field induced by application of a voltage across the junction,
m* is the effective mass, PA1 h is Boltzman's constant, PA1 PHI is the reverse barrier potential, and PA1 J is current density. PA1 1. Provide a silicon substrate, (typically, but not necessarily, of (100) crystal orientation), with alternating N and P-type regions, (each typically doped ten-to-the-fifteenth per-centimeter-cubed), present therein. PA1 2. Grow silicon dioxide atop said substrate to a depth suitable for use as a gate oxide in a (MOSFET), (typically but not necessarily six-hundred (600) to three thousand (3000) angstroms). PA1 3. Apply photoresist to the surface of said silicon dioxide. PA1 4. Expose said photoresist through a mask which causes two openings to be effected therein over each N and P-type region, each of which openings is surrounded by silicon dioxide, with the silicon dioxide between each two associated openings being a gate oxide above a silicon channel region. PA1 5. Etch the silicon dioxide, preferably anisotropically, to the surface of the silicon and then continue to isotropically etch into said silicon to a depth of hundreds of angstroms to one (1) micron or more. (Note that an isotropic silicon etch will undercut the silicon dioxide laterally a length approximately equal to the depth to which said silicon is etched perpendicular to the surface of the silicon substrate. This helps effect discontinuous metal or metal-silicide deposition in step 7 supra). PA1 6. Remove said photoresist, preferably by an asher system in which plasma activated oxygen molecules effectively burn said photoresist away. PA1 7. Deposit metal and/or metal-silicide by a line-of-sight method so that it is present atop the silicon dioxide and atop the resulting open surface of said silicon, in a discontinuous, device self-delineating, manner. A workable depth in the case where chromium is utilized is eight-hundred (800) angstroms wherein, a step 6 isotropic silicon etch depth of one (1) micron or more is utilized. However, it is noted that said examples are not to be considered limiting of the invention. PA1 8. Process, (typically but not necessarily by an elevated temperature anneal), the resulting substrate so that rectifying Schottky barrier junctions are simultaneously formed between said metal or metal-silicide and said silicon with which said metal or metal-silicide is in contact, in both N and P-type silicon regions. It has been found experimentally that a four-hundred-fifty (450) degree centigrade, thirty (30) minute vacuum anneal works well when chromium is utilized. Again, said example is not to be considered limiting of the invention. PA1 1. Provide a silicon substrate, (typically, but not necessarily, of (100) crystal orientation), with alternating N and P-type regions, (each typically doped ten-to-the-fifteenth per-centimeter-cubed but not limited thereto), present therein. PA1 2. Grow silicon dioxide atop said substrate to a depth suitable for use as a gate oxide in a (MOSFET), (typically but not necessarily six-hundred (600) to three (3000) thousand angstroms). PA1 3. Deposit a layer (eg. five-thousand (5000 Angstroms or more), of gate forming metal, (eg. Chromium or preferably Aluminum), atop said Silicon Dioxide. PA1 4. Apply photoresist to the surface of said layer of gate forming metal. PA1 5. Expose said photoresist through a mask which causes two openings to be effected therein over each N and P-type region, said openings corresponding to Source and Drain regions with the space therebetween between being a channel region in the Silicon beneath the Silicon Dioxide and layer of gate forming metal. PA1 6. Etch the layer of gate forming metal and silicon dioxide, preferably anisotropically, to the surface of the silicon and optionally continue to etch into said silicon to a depth of hundreds of angstroms to one (1) micron or more. PA1 7. Remove said photoresist, preferably by an asher system in which plasma activated oxygen molecules effectively burn said photoresist away. PA1 8. Deposit a layer of silicide forming metal, so that it is present atop the layer of gate forming metal deposited in Step 3 and atop the surface of said silicon opened in step 6, (note that said metal can be the same or a different metal than that deposited in step 3). PA1 9. Process, (typically but not necessarily by an elevated temperature anneal), the resulting substrate so that rectifying Schottky barrier junctions are simultaneously formed between said layer of silicide forming metal and said silicon with which said layer of silicide forming metal is in contact, in both N and P-type Source and Drain silicon regions. It has been found experimentally that a four-hundred (400) to five-hundred (500) degree centigrade, thirty (30) minute vacuum anneal, works well when Chromium is the Schottky barrier rectifying junction forming silicide forming metal deposited in step 8. Again, said example is not to be considered limiting of the invention. PA1 10. Perform an etch to remove the any remaining silicide forming metal deposited in Step 8, which did not form a silicide. This removes all such silicide forming metal from the edges of the Silicon Dioxide which was etched in Step 6. The layer of gate forming metal deposited in Step 3 remains atop the gate silicon dioxide, thereby providing a delineated (MOSFET) structure. PA1 1. Providing a silicon substrate; PA1 2. Growing silicon dioxide atop the surface thereof; PA1 3. Etching through said silicon dioxide and into said silicon, a pattern comprising a (MOSFET) Source and Drain separated by a semiconductorr channel region; PA1 3a. Depositing a layer of silicon protecting material such as silicon nitride and etching a pattern therein such that it remains at the ends of the channel region in the silicon. PA1 4. Growing a layer of insulating silicon dioxide atop the etched open silicon regions; PA1 4a. Removing remaining silicon protective material to provide access to silicon at the ends of said silicon channel region and proceeding directly to Step 6. PA1 5. Etching said layer of insulating silicon dioxide to open the silicon in the etched silicon regions only at positions adjacent to the Source and Drain at the ends of said channel region in said silicon; PA1 6. Depositing a layer of silicide forming metal over the resulting substrate surface, preferably by a non-line-of-sight approach such as sputtering; PA1 7. Processing the resulting system so that Schottky barrier junctions form between the deposited silicide forming metal and the opened silicon in the Source and Drain regions at the facing ends of said channel in the silicon; PA1 8. Etching away remaining unreacted silicide forming metal; PA1 9. Depositing conductor metal over the resulting substrate surface, (eg. aluminum); and PA1 10. Etching said conductor metal to form isolated Source, Drain and Gate.
The Lepselter et al. article is incorporated by reference herein. Many texts describe Schottky barrier junctions and they will not be further discussed in this Disclosure.
Continuing, a recent Patent to Honma et al., U.S. Pat. No. 5,177,568 describes a tunnel injection type semiconductor device having a Metal-Insulator-Silicon (MIS) structure comprising a semiconductor region, a source, a drain and a gate electrode wherein said source and drain are composed of a metal or metal compound member, respectively, and wherein both have an overlapping portion with said gate electrode. The Source provides a Schottky barrier junction to said semiconductor region while said drain provides an non-rectifying contact to said semiconductor region. A tunneling current is caused to flow across a Schottky barrier junction between said source and said drain, controlled by a gate voltage. This Patent describes formation of a (CMOS) device system wherein schottky barriers serve as source region contacts to N and P-type silicon and wherein interconnected drain contacts are non-rectifying. The devices described in this Patent are very interesting, but fabrication thereof obviously requires rather complicated channel region doping profile effecting and yield reducing steps to effect rectifying junctions at the source and non-rectifying junctions at the drain of a (MOSFET) structure. That is, economic savings as compared to conventional diffused junction (MOSFET) fabrication would seem to be reduced by the channel doping requirements. Use of doping and varying band gap materials are disclosed as approaches to realizing the device described. It is also noted that the devices described apparently operate, (show gate controlled drain current flow), with the semiconductor between source and drain "accumulated" while a source Schottky barrier junction is reverse biased by applied drain to source voltage polarity. That is for a N-type substrate, a positive gate to source voltage is applied and for a P-type semiconductor a negative polarity gate to source voltage would be applied. As will he seen in following Sections herein, present invention devices preferably operate by effecting "inversion" in semiconductor between source and drain. For instance, for an N-type semiconductor the applied gate voltage during operation is negative in polarity when applied drain to source voltage is positive in polarity. For P-type semiconductor the applied gate to source voltage polarity during operation is positive while the drain to source voltage polarity is negative. This is cited as a major distinction in operational bases between the Honma et al. devices and the present invention devices.
A Patent to Koeneke et al., U.S. Pat. No. 4,485,550 describes MOS and (CMOS) devices in which selective doping of regions surrounding Schottky barrier source and drain improves the operational characteristics of Schottky barrier MOS devices. The doping serves to reduce leakage current to the substrate in which said devices are fabricated and to increase current injected into the channel region. The later effect is at least partially due to the elimination of a gap between the channel region and Schottky barrier junctions at source and drain. Two problems inherrent in Schottky barrier (MOSFET) fabrication are thus attacked by the 550 Patent devices.
A Patent to Lepselter, U.S. Pat. No. 4,300,152 describes a (CMOS) device in which at least one of the N and P-Channel devices is a Schottky barrier based device. It is taught that a (CMOS) device system utilizing such is immune to latch-up based upon Silicon Controlled Rectifier-like action in (CMOS) device systems.
A Patent to Mihara et al., U.S. Pat. No. 5,049,953 describes a Schottky barrier device in which a shield layer of a second conductivity type imposed between a Schottky barrier and a substrate serves to reduce leakage current.
No known reference, however, teaches, as does the present invention disclosure, that a relatively simple fabrication procedure utilizing both N and P-type semiconductor can simultaneously efficiently form low, insulator effected, leakage current balanced Schottky barrier rectifying junctions in (MOSFET) Source and Drain regions on both said N and P-type semiconductor, preferably in a single semiconductor substrate, thereby allowing essentially balanced complimentary N and P-channel (MOSFETS) with Schottky barrier junctions at both source and drain to be easily achieved, particularly on a single substrate. This is a very significant point as it would not be obvious to one skilled in the art that such a single simultaneous procedure should exist or what elements, (eg. metal, metal-silicide and semiconductor), should be utilized in said procedure or what the procedure should be followed. The present invention provides missing teachings along with documented experimental results supporting said teachings. The present invention, however, goes even further and teaches that a single device equivalent to (CMOS) can be achieved on a single dopant type, or even intrinsic, semiconductor substrate utilizing Schottky barrier technology, with or without leakage current reducing insulator material presence, by provision of a voltage monitoring contact to the channel region under the gate electrode of a Schottky barrier (MOSFET) structure. As described elsewhere in this disclosure, said device operates because Schottky barriers formed using appropriate semiconductors and metals and/or metal silicides form rectifying junctions with either N or P-type semiconductor, and effective (MOSFET) channel region semiconductor doping can be effected by application of a gate voltage in a (MOSFET) structure. All known (CMOS) devices require the presence of N and P-type doped semiconductor. The present invention teaches that a single device equivalent to (CMOS), in contrast, requires only a single type, (N or P-type), semiconductor substrate be present, emphasis added. This enables cost savings and improved fabrication efficiency.
It is mentioned that in a proprietory report, dated Jan. 10, 1991, which was prepared by the National Institute of Standards and Technology, (NIST) in support of the grant which has funded work leading to the disclosure herein, it was concluded that the present invention could have an impact on energy conservation and utilization and that if the projected performance of the invention can be achieved, then commercial success seems assured. Said proprietory NIST report focused upon the use of chromium deposited onto both N and P-type silicon and a common anneal procedure to for Schottky barrier (MOSFETS) with rectifying junctions at both source and drain. Said NIST report was provided in response to a confidential application for grant funds submitted to the agency which is funding the present work, (the United States Department of Energy), years earlier by the inventor herein, in search of support to allow actual present invention reduction to practice.
The present invention teaches workable systems and recommended fabrication procedures therefore.